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• Byte/Word Extension
  The Byte/Word eXtensions were first introduced in the [[Processors#EV56|EV56]] and has been available in all subsequent models. The instructio
  1 KB (164 words) - 18:11, 29 August 2019
• Motion Video Instructions
  Beginning with the [[Processors#PCA56|PCA56]] processor, [[Digital|DEC]] added the Motion Video Instruction ...instruction must separate MVIs to prevent stalling. On the out-of-order [[Processors#EV6|EV6]] and newer, MVIs have a latency of 3 cycles and are slotted U0<ref
  4 KB (627 words) - 18:17, 29 August 2019
• Floating-Point Instruction Extension
  Initially implemented in the [[Processors#EV6|EV6]] processor, the Floating-Point Instruction Extension adds nine ins On previous generations, such as the [[Processors#EV5|EV5]], in order to copy data from a floating-point register to an integ
  3 KB (498 words) - 18:22, 29 August 2019
• Count Instruction Extension
  Initially implemented in the [[Processors#EV67|EV67]] processor, the Count Instruction Extension adds three instructi
  834 bytes (109 words) - 18:25, 29 August 2019
• AlphaServer DS20L
  * Dual 833 MHz [[Processors#EV68AL|EV68ALs]] with 4MB external L2 cache each
  4 KB (685 words) - 06:32, 30 August 2019
• AlphaStation XP1000
  ** 500MHz [[Processors#EV6|EV6]] or 667MHz [[Processors#EV67|EV67]] with 4MB L2 cache
  3 KB (410 words) - 06:44, 30 August 2019
• UP2700
  ...aspian chipset and dual Slot B [[Wikipedia:Alpha_21264#Alpha_21264B|EV68]] processors exceeding 1 GHz. API also planned support for up to 8GB of 200 MHz DDR SDRA
  873 bytes (127 words) - 19:19, 21 September 2019