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Table of Contents
- 1 Introduction
- 2 Basic Architecture
- 3 Instruction Formats
- 4 Instruction Descriptions
- 5 System Architecture and Programming Implications
- 6 Common PALcode Architecture
- 7 Console Subsystem Overview
- 8 Input/Output Overview
- 9 OpenVMS Alpha
- 10 Digital UNIX
- 11 Windows NT Alpha
- A Software Considerations
- B IEEE Floating-Point Conformance
- C Instruction Summary
- D Registered System and Processor Identifiers
- E Waivers and Implementation-Dependent Functionality
Figures
Tables
Preface
Introduction
- 1.1 The Alpha Approach to RISC Architecture
- 1.2 Data Format Overview
- 1.3 Instruction Format Overview
- 1.4 Instruction Overview
- 1.5 Instruction Set Characteristics
- 1.6 Terminology and Conventions
Basic Architecture
- 2.1 Addressing
- 2.2 Data Types
- 2.3 Big-Endian Addressing Support
Instruction Formats
- 3.1 Alpha Registers
- 3.2 Notation
- 3.3 Instruction Formats
Instruction Descriptions
- 4.1 Instruction Set Overview
- 4.2 Memory Integer Load/Store Instructions
- 4.3 Control Instructions
- 4.4 Integer Arithmetic Instructions
- 4.5 Logical and Shift Instructions
- 4.6 Byte Manipulation Instructions
- 4.7 Floating-Point Instructions
- 4.8 Memory Format Floating-Point Instructions
- 4.9 Branch Format Floating-Point Instructions
  - 4.9.1 Conditional Branch
- 4.10 Floating-Point Operate Format Instructions
- 4.11 Miscellaneous Instructions
- 4.12 VAX Compatibility Instructions
  - 4.12.1 VAX Compatibility Instructions
- 4.13 Multimedia (Graphics and Video) Support
System Architecture and Programming Implications
- 5.1 Introduction
- 5.2 Physical Address Space Characteristics
- 5.3 Translation Buffers and Virtual Caches
- 5.4 Caches and Write Buffers
- 5.5 Data Sharing
- 5.6 Read/Write Ordering
- 5.7 Arithmetic Traps
Common PALcode Architecture
- 6.1 PALcode
- 6.2 PALcode Instructions and Functions
- 6.3 PALcode Environment
- 6.4 Special Functions Required for PALcode
- 6.5 PALcode Effects on System Code
- 6.6 PALcode Replacement
- 6.7 Required PALcode Instructions
Console Subsystem Overview
Input/Output Overview
OpenVMS Alpha
- 9.1 Unprivileged OpenVMS Alpha PALcode
- 9.2 Privileged OpenVMS Alpha Palcode
Digital UNIX
- 10.1 Unprivileged Digital UNIX PALcode
- 10.2 Privileged Digital UNIX PALcode
Windows NT Alpha
- 11.1 Unprivileged Windows NT Alpha PALcode
- 11.2 Privileged Windows NT Alpha PALcode
Software Considerations
- A.1 Hardware-Software Compact
- A.2 Instruction-Stream Considerations
- A.3 Data-Stream Considerations
- A.4 Code Sequences
- A.5 Timing Considerations: Atomic Sequences
IEEE Floating-Point Conformance
- B.1 Alpha Choices for IEEE Options
- B.2 Alpha Support for OS Completion Handlers
  - B.2.1 IEEE Floating-Point Control (FP_C) Quadword
- B.3 Mapping to IEEE Standard
Instruction Summary
- C.1 Common Architecture Instruction Summary
- C.2 IEEE Floating-Point Instructions
- C.3 VAX Floating-Point Instructions
- C.4 Independent Floating-Point Instructions
- C.5 Opcode Summary
- C.6 Common Architecture Opcodes in Numerical Order
- C.7 OpenVMS Alpha PALcode Instruction Summary
- C.8 DIGITAL UNIX PALcode Instruction Summary
- C.9 Windows NT Alpha Instruction Summary
- C.10 PALcode Opcodes in Numerical Order
- C.11 Required PALcode Opcodes
- C.12 Opcodes Reserved to PALcode
- C.13 Opcodes Reserved to Compaq
- C.14 Unused Function Code Behavior
- C.15 ASCII Character Set
Registered System and Processor Identifiers
- D.1 Processor Type Assignments
- D.2 PALcode Variation Assignments
- D.3 Architecture Mask and Implementation Values
Waivers and Implementation-Dependent Functionality
- E.1 Waivers
- E.2 Implementation-Specific Functionality
Index
- A
- B
- C
- D
- E
- F
- G
- H
- I
- J
- L
- M
- N
- O
- P
- Q
- R
- S
- T
- U
- V
- W
- X
- Y
- Z

Pages 1--371 from Untitled Document

Page 1 2
Compaq Computer Corporation
Alpha Architecture Handbook
Order Number: EC� QD2KC� TE

Revision/ Update Information: This is Version 4 of the Alpha
Architecture Handbook. 1
1 Page 2 3
October 1998
The information in this publication is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL
ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAM-AGES
RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS
INFORMATION IS PROVIDED "AS IS" AND COMPAQ COMPUTER CORPORATION DISCLAIMS ANY
WARRANTIES, EXPRESS, IMPLIED OR STATUTORY AND EXPRESSLY DISCLAIMS THE IMPLIED WAR-RANTIES
OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST
INFRINGEMENT.

This publication contains information protected by copyright. No part of this publication may be photocopied or
reproduced in any form without prior written consent from Compaq Computer Corporation.

� Compaq Computer Corporation 1998.
All rights reserved. Printed in the U. S. A.

The following are trademarks of Comaq Computer Corporation: Alpha AXP, AXP, DEC, DIGITAL, DIGITAL
UNIX, OpenVMS, PDP� 11, VAX, VAX DOCUMENT, and the DIGITAL logo.

Cray is a registered trademark of Cray Research, Inc. IBM is a registered trademark of International Business
Machines Corporation. UNIX is a registered trademark in the United States and other countries licensed exclusively
through X/ Open Company Ltd. Windows NT is a trademark of Microsoft Corporation.

All other trademarks and registered trademarks are the property of their respective owners. 2
2 Page 3 4

7 Console Subsystem Overview
8 Input/ Output Overview
9 OpenVMS Alpha
9.1 Unprivileged OpenVMS Alpha PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9� 1
9.2 Privileged OpenVMS Alpha Palcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9� 8

10 Digital UNIX
10. 1 Unprivileged Digital UNIX PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10� 1
10. 2 Privileged Digital UNIX PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10� 2

11 Windows NT Alpha
11. 1 Unprivileged Windows NT Alpha PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11� 1
11. 2 Privileged Windows NT Alpha PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11� 2

D Registered System and Processor Identifiers
D. 1 Processor Type Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D� 1
D. 2 PALcode Variation Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D� 2
D. 3 Architecture Mask and Implementation Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D� 3

Index 10
10 Page 11 12

References in this handbook to the Alpha Architecture Reference Manual are to the Third Edition of
that manual, EY-W938E-DP. 15
15 Page 16 17
16
16 Page 17 18
Introduction 1� 1
Chapter 1
Introduction

Alpha is a 64-bit load/ store RISC architecture that is designed with particular emphasis on the
three elements that most affect performance: clock speed, multiple instruction issue, and multi-ple
processors.

The Alpha architects examined and analyzed current and theoretical RISC architecture design
elements and developed high-performance alternatives for the Alpha architecture. The archi-tects
adopted only those design elements that appeared valuable for a projected 25-year design
horizon. Thus, Alpha becomes the first 21st century computer architecture.

The Alpha architecture is designed to avoid bias toward any particular operating system or pro-gramming
language. Alpha supports the OpenVMS Alpha, DIGITAL UNIX, and Windows NT
Alpha operating systems and supports simple software migration for applications that run on
those operating systems.

This manual describes in detail how Alpha is designed to be the leadership 64-bit architecture
of the computer industry.

1.1 The Alpha Approach to RISC Architecture
Alpha Is a True 64-Bit Architecture
Alpha was designed as a 64-bit architecture. All registers are 64 bits in length and all opera-tions
are performed between 64-bit registers. It is not a 32-bit architecture that was later
expanded to 64 bits.

Alpha Is Designed for Very High-Speed Implementations
The instructions are very simple. All instructions are 32 bits in length. Memory operations are
either loads or stores. All data manipulation is done between registers.

The Alpha architecture facilitates pipelining multiple instances of the same operations because
there are no special registers and no condition codes.

The instructions interact with each other only by one instruction writing a register or memory
and another instruction reading from the same place. That makes it particularly easy to build
implementations that issue multiple instructions every CPU cycle. 17
17 Page 18 19
1� 2 Alpha Architecture Handbook
Alpha makes it easy to maintain binary compatibility across multiple implementations and easy
to maintain full speed on multiple-issue implementations. For example, there are no implemen-tation-
specific pipeline timing hazards, no load-delay slots, and no branch-delay slots.

The Alpha Approach to Byte Manipulation
The Alpha architecture reads and writes bytes between registers and memory with the LDBU
and STB instructions. (Alpha also supports word read/ writes with the LDWU and STW
instructions.)

Byte shifting and masking is performed with normal 64-bit register-to-register instructions,
crafted to keep instruction sequences short.

The Alpha Approach to Multiprocessor Shared Memory
As viewed from a second processor (including an I/ O device), a sequence of reads and writes
issued by one processor may be arbitrarily reordered by an implementation. This allows imple-mentations
to use multibank caches, bypassed write buffers, write merging, pipelined writes
with retry on error, and so forth. If strict ordering between two accesses must be maintained,
explicit memory barrier instructions can be inserted in the program.

The basic multiprocessor interlocking primitive is a RISC-style load_ locked, modify,
store_ conditional sequence. If the sequence runs without interrupt, exception, or an interfering
write from another processor, then the conditional store succeeds. Otherwise, the store fails and
the program eventually must branch back and retry the sequence. This style of interlocking
scales well with very fast caches and makes Alpha an especially attractive architecture for
building multiple-processor systems.

Alpha Instructions Include Hints for Achieving Higher Speed
A number of Alpha instructions include hints for implementations, all aimed at achieving
higher speed.

� Calculated jump instructions have a target hint that can allow much faster subroutine calls and returns.

� There are prefetching hints for the memory system that can allow much higher cache hit rates.
� There are granularity hints for the virtual-address mapping that can allow much more effective use of translation lookaside buffers for large contiguous structures.

PALcode � Alpha's Very Flexible Privileged Software Library
A Privileged Architecture Library (PALcode) is a set of subroutines that are specific to a par-ticular
Alpha operating system implementation. These subroutines provide operating-system
primitives for context switching, interrupts, exceptions, and memory management. PALcode is
similar to the BIOS libraries that are provided in personal computers.

PALcode subroutines are invoked by implementation hardware or by software CALL_ PAL
instructions. 18
18 Page 19 20
Introduction 1� 3
PALcode is written in standard machine code with some implementation-specific extensions to
provide access to low-level hardware.

PALcode lets Alpha implementations run the full OpenVMS Alpha, DIGITAL UNIX, and
Windows NT Alpha operating systems. PALcode can provide this functionality with little
overhead. For example, the OpenVMS Alpha PALcode instructions let Alpha run OpenVMS
with little more hardware than that found on a conventional RISC machine: the PAL mode bit
itself, plus four extra protection bits in each translation buffer entry.

Other versions of PALcode can be developed for real-time, teaching, and other applications.
PALcode makes Alpha an especially attractive architecture for multiple operating systems.

Alpha and Programming Languages
Alpha is an attractive architecture for compiling a large variety of programming languages.
Alpha has been carefully designed to avoid bias toward one or two programming languages.
For example:

� Alpha does not contain a subroutine call instruction that moves a register window by a fixed amount. Thus, Alpha is a good match for programming languages with many

parameters and programming languages with no parameters.
� Alpha does not contain a global integer overflow enable bit. Such a bit would need to be changed at every subroutine boundary when a FORTRAN program calls a C pro-gram.

1.2 Data Format Overview
Alpha is a load/ store RISC architecture with the following data characteristics:
� All operations are done between 64-bit registers.
� Memory is accessed via 64-bit virtual byte addresses, using the little-endian or, option-ally, the big-endian byte numbering convention.

� There are 32 integer registers and 32 floating-point registers.
� Longword (32-bit) and quadword (64-bit) integers are supported.
� Five floating-point data types are supported:
� VAX F_ floating (32-bit)
� VAX G_ floating (64-bit)
� IEEE single (32-bit)
� IEEE double (64-bit)
� IEEE extended (128-bit) 19
19 Page 20 21

1� 4 Alpha Architecture Handbook
1.3 Instruction Format Overview
As shown in Figure 1� 1, Alpha instructions are all 32 bits in length. There are four major
instruction format classes that contain 0, 1, 2, or 3 register fields. All formats have a 6-bit
opcode.

Figure 1� 1: Instruction Format Overview

� PALcode instructions specify, in the function code field, one of a few dozen complex operations to be performed.
� Conditional branch instructions test register Ra and specify a signed 21-bit PC-rela-tive longword target displacement. Subroutine calls put the return address in register
Ra.
� Load and store instructions move bytes, words, longwords, or quadwords between register Ra and memory, using Rb plus a signed 16-bit displacement as the memory

address.
� Operate instructions for floating-point and integer operations are both represented in Figure 1� 1 by the operate format illustration and are as follows:

� Word and byte sign-extension operators.
� Floating-point operations use Ra and Rb as source registers and write the result in
register Rc. There is an 11-bit extended opcode in the function field.

� Integer operations use Ra and Rb or an 8-bit literal as the source operand, and write
the result in register Rc.

� Integer operate instructions can use the Rb field and part of the function field to
specify an 8-bit literal. There is a 7-bit extended opcode in the function field.

1. 4 Instruction Overview
PALcode Instructions
As described in Section 1. 1, a Privileged Architecture Library (PALcode) is a set of subrou-tines
that is specific to a particular Alpha operating-system implementation. These subroutines
can be invoked by hardware or by software CALL_ PAL instructions, which use the function
field to vector to the specified subroutine.

0 31 26 25 21 20 16 15 5 4
Number Opcode

Opcode
Opcode
Opcode

Disp
Disp
Function RC RB
RB
RA
RA
RA
PALcode Format
Branch Format
Memory Format
Operate Format 20
20 Page 21 22
Introduction 1� 5
Branch Instructions
Conditional branch instructions can test a register for positive/ negative or for zero/ nonzero,
and they can test integer registers for even/ odd. Unconditional branch instructions can write a
return address into a register.

There is also a calculated jump instruction that branches to an arbitrary 64-bit address in a
register.

Load/ Store Instructions
Load and store instructions move 8-bit, 16-bit, 32-bit, or 64-bit aligned quantities from and to
memory. Memory addresses are flat 64-bit virtual addresses with no segmentation.

The VAX floating-point load/ store instructions swap words to give a consistent register format
for floating-point operations.

A 32-bit integer datum is placed in a register in a canonical form that makes 33 copies of the
high bit of the datum. A 32-bit floating-point datum is placed in a register in a canonical form
that extends the exponent by 3 bits and extends the fraction with 29 low-order zeros. The 32-bit
operates preserve these canonical forms.

Compilers, as directed by user declarations, can generate any mixture of 32-bit and 64-bit oper-ations.
The Alpha architecture has no 32/ 64 mode bit.

Integer Operate Instructions
The integer operate instructions manipulate full 64-bit values and include the usual assortment
of arithmetic, compare, logical, and shift instructions.

There are just three 32-bit integer operates: add, subtract, and multiply. They differ from their
64-bit counterparts only in overflow detection and in producing 32-bit canonical results.

There is no integer divide instruction.
The Alpha architecture also supports the following additional operations:
� Scaled add/ subtract instructions for quick subscript calculation
� 128-bit multiply for division by a constant, and multiprecision arithmetic
� Conditional move instructions for avoiding branch instructions
� An extensive set of in-register byte and word manipulation instructions
� A set of multimedia instructions that support graphics and video
Integer overflow trap enable is encoded in the function field of each instruction, rather than
kept in a global state bit. Thus, for example, both ADDQ/ V and ADDQ opcodes exist for spec-ifying
64-bit ADD with and without overflow checking. That makes it easier to pipeline
implementations. 21
21 Page 22 23
1� 6 Alpha Architecture Handbook
Floating-Point Operate Instructions
The floating-point operate instructions include four complete sets of VAX and IEEE arith-metic
instructions, plus instructions for performing conversions between floating-point and
integer quantities.

In addition to the operations found in conventional RISC architectures, Alpha includes condi-tional
move instructions for avoiding branches and merge sign/ exponent instructions for simple
field manipulation.

The arithmetic trap enables and rounding mode are encoded in the function field of each
instruction, rather than kept in global state bits. That makes it easier to pipeline
implementations.

1. 5 Instruction Set Characteristics
Alpha instruction set characteristics are as follows:
� All instructions are 32 bits long and have a regular format.
� There are 32 integer registers (R0 through R31), each 64 bits wide. R31 reads as zero, and writes to R31 are ignored.

� All integer data manipulation is between integer registers, with up to two variable regis-ter source operands (one may be an 8-bit literal) and one register destination operand.
� There are 32 floating-point registers (F0 through F31), each 64 bits wide. F31 reads as zero, and writes to F31 are ignored.
� All floating-point data manipulation is between floating-point registers, with up to two register source operands and one register destination operand.
� Instructions can move data in an integer register file to a floating-point register file, and data in a floating-point register file to an integer register file. The instructions do not
interpret bits in the register files and do not access memory.
� All memory reference instructions are of the load/ store type that moves data between registers and memory.

� There are no branch condition codes. Branch instructions test an integer or floating-point register value, which may be the result of a previous compare.
� Integer and logical instructions operate on quadwords.
� Floating-point instructions operate on G_ floating, F_ floating, and IEEE extended, dou-ble, and single operands. D_ floating "format compatibility," in which binary files of

D_ floating numbers may be processed, but without the last 3 bits of fraction precision,
is also provided.

� A minimal number of VAX compatibility instructions are included.

1. 6 Terminology and Conventions
The following sections describe the terminology and conventions used in this book. 22
22 Page 23 24
Introduction 1� 7
1.6. 1 Numbering
All numbers are decimal unless otherwise indicated. Where there is ambiguity, numbers other
than decimal are indicated with the name of the base in subscript form, for example, 10 16.

1.6. 2 Security Holes
A security hole is an error of commission, omission, or oversight in a system that allows pro-tection
mechanisms to be bypassed.

Security holes exist when unprivileged software (software running outside of kernel mode)
can:

� Affect the operation of another process without authorization from the operating sys-tem;

� Amplify its privilege without authorization from the operating system; or
� Communicate with another process, either overtly or covertly, without authorization from the operating system.

The Alpha architecture has been designed to contain no architectural security holes. Hardware
(processors, buses, controllers, and so on) and software should likewise be designed to avoid
security holes.

1.6. 3 UNPREDICTABLE and UNDEFINED
The terms UNPREDICTABLE and UNDEFINED are used throughout this book. Their mean-ings
are quite different and must be carefully distinguished.

In particular, only privileged software (software running in kernel mode) can trigger UNDE-FINED
operations. Unprivileged software cannot trigger UNDEFINED operations. However,
either privileged or unprivileged software can trigger UNPREDICTABLE results or
occurrences.

UNPREDICTABLE results or occurrences do not disrupt the basic operation of the processor;
it continues to execute instructions in its normal manner. In contrast, UNDEFINED operation
can halt the processor or cause it to lose information.

The terms UNPREDICTABLE and UNDEFINED can be further described as follows:

UNPREDICTABLE
� Results or occurrences specified as UNPREDICTABLE may vary from moment to moment, implementation to implementation, and instruction to instruction within

implementations. Software can never depend on results specified as UNPREDICT-ABLE.

� An UNPREDICTABLE result may acquire an arbitrary value subject to a few con-straints. Such a result may be an arbitrary function of the input operands or of any state
information that is accessible to the process in its current access mode. UNPREDICT-ABLE
results may be unchanged from their previous values. 23
23 Page 24 25
1� 8 Alpha Architecture Handbook
Operations that produce UNPREDICTABLE results may also produce exceptions.
� An occurrence specified as UNPREDICTABLE may happen or not based on an arbi-trary choice function. The choice function is subject to the same constraints as are

UNPREDICTABLE results and, in particular, must not constitute a security hole.
Specifically, UNPREDICTABLE results must not depend upon, or be a function of,
the contents of memory locations or registers that are inaccessible to the current
process in the current access mode.

Also, operations that may produce UNPREDICTABLE results must not:
� Write or modify the contents of memory locations or registers to which the current
process in the current access mode does not have access, or

� Halt or hang the system or any of its components.
For example, a security hole would exist if some UNPREDICTABLE result depended
on the value of a register in another process, on the contents of processor temporary
registers left behind by some previously running process, or on a sequence of actions
of different processes.

UNDEFINED
� Operations specified as UNDEFINED may vary from moment to moment, implementa-tion to implementation, and instruction to instruction within implementations. The

operation may vary in effect from nothing to stopping system operation.
� UNDEFINED operations may halt the processor or cause it to lose information. How-ever, UNDEFINED operations must not cause the processor to hang, that is, reach an

unhalted state from which there is no transition to a normal state in which the machine
executes instructions.

1.6. 4 Ranges and Extents
Ranges are specified by a pair of numbers separated by two periods and are inclusive. For
example, a range of integers 0.. 4 includes the integers 0, 1, 2, 3, and 4.

Extents are specified by a pair of numbers in angle brackets separated by a colon and are inclu-sive.
For example, bits <7: 3> specify an extent of bits including bits 7, 6, 5, 4, and 3.

1.6. 5 ALIGNED and UNALIGNED
In this document the terms ALIGNED and NATURALLY ALIGNED are used interchange-ably
to refer to data objects that are powers of two in size. An aligned datum of size 2** N is
stored in memory at a byte address that is a multiple of 2** N, that is, one that has N low-order
zeros. Thus, an aligned 64-byte stack frame has a memory address that is a multiple of 64.

If a datum of size 2** N is stored at a byte address that is not a multiple of 2** N, it is called
UNALIGNED. 24
24 Page 25 26

Introduction 1� 9
1.6. 6 Must Be Zero (MBZ)
Fields specified as Must be Zero (MBZ) must never be filled by software with a non-zero
value. These fields may be used at some future time. If the processor encounters a non-zero
value in a field specified as MBZ, an Illegal Operand exception occurs.

1.6. 7 Read As Zero (RAZ)
Fields specified as Read as Zero (RAZ) return a zero when read.

1.6. 8 Should Be Zero (SBZ)
Fields specified as Should be Zero (SBZ) should be filled by software with a zero value. Non-zero
values in SBZ fields produce UNPREDICTABLE results and may produce extraneous
instruction-issue delays.

1.6. 9 Ignore (IGN)
Fields specified as Ignore (IGN) are ignored when written.

1.6. 10 Implementation Dependent (IMP)
Fields specified as Implementation Dependent (IMP) may be used for implementation-specific
purposes. Each implementation must document fully the behavior of all fields marked as IMP
by the Alpha specification.

1.6. 11 Illustration Conventions
Illustrations that depict registers or memory follow the convention that increasing addresses
run right to left and top to bottom.

1.6. 12 Macro Code Example Conventions
All instructions in macro code examples are either listed in Chapter 4 or are stylized code
forms found in Section A. 4. 6. 25
25 Page 26 27
26
26 Page 27 28

Basic Architecture 2� 1
Chapter 2
Basic Architecture

2.1 Addressing
The basic addressable unit in the Alpha architecture is the 8-bit byte. Virtual addresses are 64
bits long. An implementation may support a smaller virtual address space. The minimum vir-tual
address size is 43 bits.

Virtual addresses as seen by the program are translated into physical memory addresses by the
memory management mechanism.

Although the data types in Section 2.2 are described in terms of little-endian byte addressing,
implementations may also include big-endian addressing support, as described in Section 2. 3.
All current implementations have some big-endian support.

2.2 Data Types
Following are descriptions of the Alpha architecture data types.

2. 2.1 Byte
A byte is 8 contiguous bits starting on an addressable byte boundary. The bits are numbered
from right to left, 0 through 7, as shown in Figure 2� 1.

Figure 2� 1: Byte Format

A byte is specified by its address A. A byte is an 8-bit value. The byte is only supported in
Alpha by the load, store, sign-extend, extract, mask, insert, and zap instructions.

2.2. 2 Word
A word is 2 contiguous bytes starting on an arbitrary byte boundary. The bits are numbered
from right to left, 0 through 15, as shown in Figure 2� 2.

7 0
:A 27
27 Page 28 29

2� 2 Alpha Architecture Handbook
Figure 2� 2: Word Format
A word is specified by its address, the address of the byte containing bit 0.
A word is a 16-bit value. The word is only supported in Alpha by the load, store, sign-extend,
extract, mask, and insert instructions.

2.2. 3 Longword
A longword is 4 contiguous bytes starting on an arbitrary byte boundary. The bits are num-bered
from right to left, 0 through 31, as shown in Figure 2� 3.

Figure 2� 3: Longword Format

A longword is specified by its address A, the address of the byte containing bit 0. A longword
is a 32-bit value.

When interpreted arithmetically, a longword is a two's-complement integer with bits of
increasing significance from 0 through 30. Bit 31 is the sign bit. The longword is only sup-ported
in Alpha by sign-extended load and store instructions and by longword arithmetic
instructions.

Note:
Alpha implementations will impose a significant performance penalty when accessing
longword operands that are not naturally aligned. (A naturally aligned longword has zero
as the low-order two bits of its address.)

2.2. 4 Quadword
A quadword is 8 contiguous bytes starting on an arbitrary byte boundary. The bits are num-bered
from right to left, 0 through 63, as shown in Figure 2� 4.

Figure 2� 4: Quadword Format

0 15
:A

0 31
:A

63 0
:A 28
28 Page 29 30

Basic Architecture 2� 3
A quadword is specified by its address A, the address of the byte containing bit 0. A quadword
is a 64-bit value. When interpreted arithmetically, a quadword is either a two's-complement
integer with bits of increasing significance from 0 through 62 and bit 63 as the sign bit, or an
unsigned integer with bits of increasing significance from 0 through 63.

Note:
Alpha implementations will impose a significant performance penalty when accessing
quadword operands that are not naturally aligned. (A naturally aligned quadword has zero
as the low-order three bits of its address.)

2.2. 5 VAX Floating-Point Formats
VAX floating-point numbers are stored in one set of formats in memory and in a second set of
formats in registers. The floating-point load and store instructions convert between these for-mats
purely by rearranging bits; no rounding or range-checking is done by the load and store
instructions.

2.2.5.1 F_ floating
An F_ floating datum is 4 contiguous bytes in memory starting on an arbitrary byte boundary.
The bits are labeled from right to left, 0 through 31, as shown in Figure 2� 5 .

Figure 2� 5: F_ floating Datum

An F_ floating operand occupies 64 bits in a floating register, left-justified in the 64-bit regis-ter,
as shown in Figure 2� 6.

Figure 2� 6: F_ floating Register Format

The F_ floating load instruction reorders bits on the way in from memory, expands the expo-nent
from 8 to 11 bits, and sets the low-order fraction bits to zero. This produces in the register
an equivalent G_ floating number suitable for either F_ floating or G_ floating operations. The
mapping from 8-bit memory-format exponents to 11-bit register-format exponents is shown in
Table 2� 1. This mapping preserves both normal values and exceptional values.

S Frac. Hi Fraction Lo :A Exp.
6 0 7 15 16 14 31

0 63 62
S
52 51 29 28
Exp. Fraction 0 :Fx 29
29 Page 30 31

2� 4 Alpha Architecture Handbook
The F_ floating store instruction reorders register bits on the way to memory and does no
checking of the low-order fraction bits. Register bits <61: 59> and <28: 0>