Maurice Hilarius wrote:
>
> With regards to your message at 12:35 PM 11/3/00, W Bauske. Where you stated:
> >It appears my dual PIII motherboard also uses interrupts above 15:
> >
> > CPU0 CPU1
> > 0: 12903677 14055458 IO-APIC-edge timer
> > 1: 1815 1917 IO-APIC-edge keyboard
> > 2: 0 0 XT-PIC cascade
> > 12: 522 96 IO-APIC-edge PS/2 Mouse
> > 13: 0 0 XT-PIC fpu
> > 14: 33744 26522 IO-APIC-edge ide0
> > 15: 60 51 IO-APIC-edge ide1
> > 18: 138908 135458 IO-APIC-level eth0
> > 20: 152 152 IO-APIC-level ide4, ide5
> > 22: 23588 23422 IO-APIC-level ide2
> >
> >So I suppose it would have similar problems with such cards. Course
> >it doesn't do sound or modems.... Only disks.
> Actually it doesn't.
> It has 2 PCI buses. One is using the first 16 interrupts, the other the
> next 16. Still, all cards are getting 4 bit addresses.
> The BIOS reports numbers like this so they are distinguishable. Ultimately
> it all maps to one PCI controller through a PCI-PCI bridge chip.
> UP2K does the same, but is capable of assigning interrupts to much wider
> range of numbers.
> Note on your UP2K the one line:
> 47: 125946091 0 eth0
>
> That's IRQ 47.
> Do you see any IRQ #'s reported above 32 on the P3 box?
>
Nope. Just surprised me when I saw them that way.
Makes sense they could be split across the two processors
but I thought PCI bridges don't generate additional IRQ's,
they just feed across the ones that they're attached to.
I'm not an EE guy so someone who knows can tell the real
story. I guess it just depends on the chipset. This PIII
uses the Serverworks LE chipset. Runs the same memory as
a UP2K/XP1000. I don't remember if it has two PCI bus
segments or not. I know it has both 64bit and 32bit slots
so maybe they're separated that way?? Also, if they're
split, how come both cpus can service all the interrupts?
Must be something related to that IO-APIC description...
This is a little off topic but I thought the comparison
was interesting. The lack of interrupts on the second cpu
of the UP2K I find a bit worrisome. Implies that the
interrupts aren't split so one processor is more loaded if you
do heavy I/O or network accesses. I'd prefer the overhead
be spread across both cpus. Thats because my codes assume
both cpus are equal and by only putting overhead on one
cpu, it slows BOTH cpus down to that slower level, essentially
wasting cycles on the second cpu because it can get it's
workload done more quickly than the other cpu servicing
interrupts...
Wes
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