Bjorn R. Bjornsson (brb@halo.hi.is)
Tue, 9 Mar 1999 22:05:13 +0000 (GMT)
If I read the code correctly, then few of the Alpha
systems support more than 1GB RAM running Linux with
an unmodified kernel.
However it should be fairly straightforward to support more
than 1GB of physical RAM on most Alpha systems, although
I must admit it took me quite some time to get an
AlphaServer 800 (aka Corelle) to run with more than 1GB.
PCI limitations ought not to show up until you try go past
4GB.
Following is a patch to linux/include/asm-alpha/cia_core.h
to allow the AlphaServer 800 to support 2GB of RAM (I'm
also including a uu-encoded version of the patch below).
--- linux-2.2.3/include/asm-alpha/core_cia.h Wed Jan 13 18:42:49 1999
+++ linux-2.2.3-brbkludge/include/asm-alpha/core_cia.h Tue Mar 9 21:25:01 1999
@@ -77,14 +77,49 @@
#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
+/*
+ * Kludge to enable 2GB RAM on Alphaserver 800 (Corelle).
+ * The AlphaLinux firmware/chipset/pci code is in need of a
+ * bit of rewrite, but this kludge is quick, dirty and works.
+ *
+ * It is imperative for these changes to work that that
+ * the SRM initialized PCI configuration is not preserved
+ * at boot time, ie. say NO to 'Use SRM PCI setup' during
+ * kernel config (On the AlphaServer 800, SRM always comes
+ * up with a DMA_WIN_BASE at 1GB * and DMA_WIN_SIZE of 1GB,
+ * regardless of the amount of memory).
+ *
+ * Similar KLUDGES should work for other Alpha systems, although
+ * the SX164 should support 2GB without changes.
+ * Also I see no reason why, setting the dma window at 4GB and
+ * size of 4GB, would not enable the Corelle to run with 4GB of
+ * RAM.
+ *
+ * For further info contact: Bjorn R. Bjornsson, brb@halo.hi.is
+ */
+#define BRB_2GB_KLUDGE
+#ifdef BRB_2GB_KLUDGE
+#define CIA_DMA_WIN_BASE_DEFAULT 0x80000000 /* fixed, 2G @ 2G */
+#define CIA_DMA_WIN_SIZE_DEFAULT 0x80000000 /* fixed, 2G @ 2G */
+#else
#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024)
#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024)
+#endif
+
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
#define CIA_DMA_WIN_BASE alpha_mv.dma_win_base
#define CIA_DMA_WIN_SIZE alpha_mv.dma_win_size
#else
+/*
+ * The next source line used to read:
+ *
#define CIA_DMA_WIN_BASE CIA_DMA_WIN_SIZE_DEFAULT
+ *
+ * Which is almost certainly a typo, but is literally a Freudian
+ * slip, in view of the chipset spec.
+ */
+#define CIA_DMA_WIN_BASE CIA_DMA_WIN_BASE_DEFAULT
#define CIA_DMA_WIN_SIZE CIA_DMA_WIN_SIZE_DEFAULT
#endif
@@ -553,6 +588,12 @@
#define __outw cia_outw
#define __outl cia_outl
+#ifdef BRB_2GB_KLUDGE
+#define __readb cia_readb
+#define __readw cia_readw
+#define __writeb cia_writeb
+#define __writew cia_writew
+#else
#ifdef CONFIG_ALPHA_SRM_SETUP
#define __readb cia_srm_readb
#define __readw cia_srm_readw
@@ -563,6 +604,7 @@
#define __readw cia_readw
#define __writeb cia_writeb
#define __writew cia_writew
+#endif
#endif
#define __readl cia_readl
Here is the uuencoded version:
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`
end
Bjorn R. Bjornsson
brb@halo.hi.is
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