Eh? There is no overflow bit. There is is no PSW to put one in.
Thus doing umul and umulh sequentially is your only option.
Instruction latency timings are to be found in the respective CPU
Hardware Reference Manuals. But for specific case of umulh, the
ev45 has a general 23 cycle latency (and two special bypases), while
the ev5 has a latency of 14 cycles + 2 if an operand came from Ebox.
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