RCS file: RCS/bios32.c,v
retrieving revision 1.2
diff -r1.2 bios32.c
626c626
< { 1, 1, -1, -1, -1}, /* idsel 13 KN25_PCI_SLOT2 */
---
> { 1, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
I'm running a kernel with that change and life seems to be very happy;
I'm doing general IP traffic through my eth0, with my eth1 now dealing
mostly with NFS on a private backend network. All of the network
anomalies that I reported before are gone. I've backed out of my
route_tab[] IRQ9/IRQ10 swap, since this idsel 13 change makes the
original route_tab[] give me IRQ10 first (in fact, with both hacks
installed I was getting IRQ9 again :-)
The long form:
Having done this on a wing and a prayer, I'm clearly a little concerned
that the results are specious. The stock arch/alpha/kernel/bios32.c has
this bit for Avanti PCI bus initialization:
/*
* The Noname board has 5 PCI slots with each of the 4
* interrupt pins routed to different pins on the PCI/ISA
* bridge (PIRQ0-PIRQ3). The table below is based on
* information available at:
*
* http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
*
* I have no information on the Avanti interrupt routing, but
* the routing seems to be identical to the Noname except
* that the Avanti has an additional slot whose routing I'm
* unsure of.
*
* pirq_tab[0] is a fake entry to deal with old PCI boards
* that have the interrupt pin number hardwired to 0 (meaning
* that they use the default INTA line, if they are interrupt
* driven at all).
*/
static const char pirq_tab[][5] = {
{ 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
{-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
{ 2, 2, -1, -1, -1}, /* idsel 8 (slot closest to ISA) */
{-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
{-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
{ 0, 0, 2, 1, 0}, /* idsel 11 (slot furthest from
ISA) KN25_PCI_SLOT0 */
{ 1, 1, 0, 2, 1}, /* idsel 12 (middle slot)
KN25_PCI_SLOT1 */
#ifdef CONFIG_ALPHA_AVANTI
{ 1, 1, -1, -1, -1}, /* idsel 13 KN25_PCI_SLOT2 */
#endif /* CONFIG_ALPHA_AVANTI */
};
It occurred to me that the interrupt routing for idsel 13 looked
*awfully* strange, given that the other two PCI slots had "real-looking"
entries. I went and referenced the file in the comment
(http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt), which had the
following table:
Table 5-2 PCI Interrupt routing
PCI ISA Bridge PCI
channel Source
----------------------------------
PIRQ0 PCI Slot 1 Int A
PCI Slot 2 Int B
PCI Slot 3 Int C
PCI Slot 1 Int D
PIRQ1 PCI Slot 2 Int A
PCI Slot 3 Int B
PCI Slot 1 Int C
PCI Slot 2 Int D
PIRQ2 PCI Slot 3 Int A
PCI Slot 1 Int B
PCI Slot 2 Int C
PCI Slot 3 Int D
PIRQ3 SCSI Controller
---------------------------------
Deciphering the mapping from table 5-2 to pirq_tab (PIRQn top-to-bottom
-> pirq_tab[] right-to-left, pirq_tab[][] entry = PIRQn slot - 1) implied
that there was no coded mapping for PIRQ2. Since I believed that idsel
13 didn't have valid interrupt routing, I simply mapped the PIRQ2 info
into idsel 13, leaving pirq_tab[][0] alone. Maybe I should have changed
pirq_tab[][0] from "1" to "2", since idsel 8 seems to be unused?
dp
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